BAP-1491 Three-Phase Bridge IGBT Driver
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GDB Power Supply
The AP-1491 Gate Drive Board requires either an unregulated 24 (20-30) volt or regulated 15 (14.5-15.5) volt power supply to operate (see Table 1 for pin assignments). The system designer must choose one supply or the other, whichever is available or preferred. Note: Connecting both power supplies simultaneously will create contention issues that may result in damage to the board.
The input voltage is used to generate the logic control power supplies and the required isolated bipolar power supplies for each individual IGBT. The power consumed by the 24-volt or 15-volt supply is proportional to the gate charge and the switching frequency of the IGBT being driven. The larger the IGBT in a particular manufacturer’s series, the larger the gate charge, therefore the more power it will consume.
The graph in Figure 2 depicts the estimated power consumption vs. switching frequency for a three-phase bridge configuration employing three dual IGBTs, each with a gate charge of 1100ηC. The value at zero Hz is the power consumed by the GDB before switching IGBTs of any current rating. The power consumed increases with switching frequency and is proportional to the gate charge. To determine the power required for a specific application, look up the gate charge (usually given in ηC on the data sheets) of the selected IGBT and offset the power consumed by the GDB at zero Hz by the power consumed by switching IGBTs. Note: It is not recommended to run a standard three-phase bridge, with IGBTs having a gate charge of 1500ηC, beyond 20KHz. Excessive heating of gate drive transistors may occur, resulting in potential damage to the board. Factory modifications are available to the standard board for operation up to 30KHz under the above stated conditions. Figure 8 depicts the maximum recommended frequency vs. gate charge.
The customer provided control signals that determine the IGBT conduction state require 0 volts for an OFF command and 15 volts for an ON command. The GDB can be modified to accept TTL level PWM control signals. Please refer to the FAX form at the end of this Datasheet/Application Note. These signals are referenced to the GDB power supply ground. For three-phase inverter applications, these signals are inputs into pins PWMA+, PWMA-, PWMB+, PWMB-, PWMC+ and PWMC- on connector J1 (pin assignments located in Table 1). These signals are fed through Schmitt-triggered buffers to ensure fast edges for overlap detection and dead time generation circuitry.
The overlap detection circuitry inhibits a complimentary pair of IGBTs (i.e. IGBTA+ and IGBTA- in Figure 3) from firing simultaneously, which would result in a potentially destructive shoot through current. If an overlap is detected, both the upper and lower IGBTs are held off until one of the IGBT control inputs (PWMX+ or PWMX-) go low, at which point the IGBT still commanded high will turn on.
Dead time, which is a delay from when the customer provided control signal goes high to when the on signal is applied to the gate of the IGBT, is generated on board. Therefore, dead time is neither required nor desired on the control signals. Customer provided dead time may effect the RESET function described in the Protection Features section below. Standard dead time is set to approximately 2ms, consult factory for alternate dead time settings (see APS Fax Request Form attached to the end of this Application Note).
Gate Drive Signals
After the control signals are integrated with dead time, they are optically isolated and buffered by a transistor stage with the capability to source the high peak currents necessary to turn large IGBTs on and off quickly. The GDB is equipped with 4.3-Ohm gate resistors standard that allow up to a 3 Amp peak current pulse. This resistor is selected to optimize the performance of an IGBT with a gate charge of approximately 1000hC; however, it will work in many applications. Consult factory for alternate gate resistor values.
The isolated gate drive power supplies are generated with three separate high frequency transformers. These transformers are high potential tested to 2500 volts between each of its three windings. The primary of each transformer is referenced to the ground of the 24-volt or 15-volt power supply.
Each secondary is referenced to an emitter of an IGBT in a phase. The capacitance between the secondaries is less than 15pF to minimize capacitive coupling between upper and lower IGBTs.
Each secondary creates a bipolar power supply that is optimally regulated to sufficiently drive the IGBT into saturation, yet low enough to limit short circuit currents and minimize power supply consumption. A negative bias is provided when the IGBT is off to ensure it remains off and to minimize turn off losses.
The APS GDB is specifically designed to operate with open loop Hall effect sensors. The GDB provides the necessary ±15-volt power supplies and ground reference for three separate current sensors (see Figure 4). An isolated voltage proportional to output current is fed back to the GDB where it is buffered and fed back to the customer provided controller (see Table 1 for pin assignments) as a real time analog representation of the output currents.
The gain of the signal conditioning circuitry on the GDB is set to unity. Therefore, if the Hall effect sensor’s output is 4 volts, the voltage fed back to the customer provided controller would be 4 volts. The scaling of the output current feedback, along with the over current threshold can be adjusted to a specific application. The default scaling is illustrated in Figure 9. Note: The Hall effect sensors must be mounted with its current direction arrow facing in towards the IGBT.
DC Link Voltage Sensing
The positive of the DC link should be fed back to the GDB for monitoring and protection (see Figure 3). The reference for the DC link sense wire is the emitter of the lower IGBT of phase A (EMIT A-), which is also the ground of the DC link. This voltage is attenuated by a voltage divider (100:1) and transmitted across an optical barrier to provide an isolated, logic level representation of the DC link now referenced to the ground of the GDB power supply. The attenuated voltage is available on pin 13 of J1 (600 volts on the DC link will result in 6.0 volts at pin 13) and is also used by the control logic to detect an over voltage condition (default threshold of 910 ±10 VDC).
The GDB temperature sense circuit uses an LM35, a low cost, industry standard temperature sensor available in a TO-92 package. Unlike more expensive bi-metallic thermocouples, its output is immune to electrostatic and electromagnetic fields, which will undoubtedly be present in the system.
A 4-pin header on the board, J2, provides the necessary 15 volts and ground to power the LM35. The LM35 feeds back a voltage proportional to temperature, which is scaled, buffered and available on pin 11 of J1.
The scaling of the signal on pin 11 of J1 is 1V/12°C, where 0 volts is 0°C. The over temperature threshold is set on the GDB at 98 ±2°C, which corresponds to 8.17 volts at pin 11. The threshold can be adjusted for a specific application.
The APS GDB is equipped with several protection features that will prevent catastrophic system failures. In the case of one of the faults discussed below, all gate drive signals are latched off (customer provided control signals are inhibited from reaching the gates) and the LED associated with the fault will light. The GDB will remain in a latched off state until all customer provided control signals are held low for at least 8ms. When both control signals are held low for a minimum of 8ms, the latched fault will be reset. If the cause of the fault condition is removed, the control signals will be applied to the gates and the LED will be extinguished.
This 8ms reset feature is the reason that user generated dead time is neither required nor desired. If dead time of 8ms is supplied with the control signals, the unit will not properly latch off on fault event and will continue to fire during fault conditions. If an over current fault exists, the GDB will protect itself and the IGBTs on a pulse-by-pulse basis. However, the IGBTs may not be able to turn on into this condition indefinitely. Therefore, the control logic should heed the warning of the fault signals and inhibit the control signals when a fault condition is indicated.
Over Current Protection
The first form of over current protection compares the feedback from each Hall effect sensor to a predetermined threshold. When the threshold is exceeded, all gate drive signals are latched off within 2ms. They remain latched off until the fault condition is removed and all customer provided control signals are held low for at least 8ms.
The over current threshold should be set such that the voltage overshoot, due to the DC link inductance (see System Considerations), resulting at turn off does not reach destructive levels for the IGBTs being used.
The second form of over current protection on the three-phase GDB is used only with Powerex F-series IGBTs. When an over current condition is detected, the gate-emitter voltage is reduced to limit short circuit current. The APS GDB senses this condition and performs a soft turn-off of the IGBT conducting the excessive current. This form of over current is typically a shoot through with no load impedance to limit its magnitude. Therefore, a soft turn off is necessary to limit the voltage overshoot at turn off to a safe level. Upon detection of this condition the soft turn off is performed, all gate drive signals are latched off, and the associated phase’s LED is illuminated. The gate signals remain latched off until the fault condition is removed and all customer provided control signals are held low for at least 8ms. An over current or short circuit fault output signal is annunciated for each phase leg on J1-pins 3, 6 and 9, see page 10 for additional information.
Over Voltage Protection
The over voltage protection senses the DC link input and compares it to a predetermined threshold, 910 volts for 1200 volt devices and 450 volts for 600 volt devices. When the threshold is exceeded for more than 1ms, the gate pulses are latched off 2ms later, and the over voltage LED is illuminated. The gate signals remain latched off until the fault condition is removed and all customer provided control signals are held low for at least 8ms. An over voltage fault output signal is annunciated on J1 pin 11, see page 10 for more information.
Over Temperature Protection
The over temperature protection uses the temperature sense input and compares it to a predetermined threshold, 98 ± 2°C. When the threshold is exceeded for 1ms, the gate pulses are latched off 2ms later and the over temperature LED is illuminated. The gate signals remain latched off until the temperature sense input goes below 98°C and all customer provided control signals are held low for at least 8ms. An over temperature fault output signal is annunciated on J1 pin 11, see page 10 for more information.
Under Voltage Lock Out (UVLO)
The UVLO protection monitors the 15-volt logic supply, latches off the gate pulses and illuminates the UVLO LED if the 15-volt supply dips below 12 volts.
There is also an UVLO on each gate drive chip. When the power supply for a gate drive chip droops to a value that precludes the IGBT from being driven into saturation, the gate pulses are latched off and the associated phase’s over current LED is illuminated. The gate signals remain latched off until the fault condition is removed and all customer provided control signals are held low for at least 8s. A UVLO fault output signal is annunciated on J1 pin 11, see page 10 for more information.
Connecting the APS GDB to a Three Phase System
In order for the APS GDB to interface with a power stage, several connections need to be addressed:
Ribbon Cable connector J1 – A 26 pin ribbon cable connector (3M part #3399-7600 with strain relief part #3448-3026 or an equivalent) is required to interface the GDB with the customer provided controls. Pin assignments are detailed in Table 1. If the control logic already exists without a 26-pin header, terminal block to 26-pin header adapters are available.
Gate Leads – The power stage should be packaged so the gate leads are as short as possible. The gate leads should be a twisted pair of 22 AWG wires (approximately 2-3 turns per inch) no more than two feet long, preferably 4-6 inches long. There are through holes located next to the solder pads for each gate and emitter connection on the GDB. These provide a low cost, reliable strain relief by feeding the wire through the blank hole and then soldering the wire to the pad next to it.
Standard gate lead lengths supplied are 3.5” long. Longer or shorter leads are available upon request. Please see the form at the end of this Datasheet/Application Note for additional information.
DC Link Connection – The DC link monitoring and over voltage protection are made possible by the DC link connection, which should be a single 22 AWG wire with a ring terminal on the end to connect to the positive of the DC link. This wire’s interface with the GDB uses the same strain relief technique detailed in the gate lead section above.
Current Sense Connection – The GDB provides a four-wire connection for current sensing of each of the three phases. The connections are clearly labeled on the GDB and are the required connections to interface with the HAS or HAC series of Hall Effect Sensors from LEM, or equivalent (Note: The sequence of the GDB connections for phase A is not the same as the sequence for phases B and C). To make the connections to the GDB, 22 AWG is recommended employing the strain relief technique depicted in Figure 3. However, since the four connections for each LEM have .100” spacing, many connectors may be inserted in the board. The LEM interface uses a four-pin Molex connector part # 5045-04A. The system designer may use the Molex mate or an insulation displacement connector, such as the AMP part # 640440-4, will work as well.
Temperature Sense – A 4-pin header, J2, is provided on the GDB to interface with the three terminal temperature sense. A 4-pin header is used in lieu of a three-pin header to provide additional structural integrity and the same connector, AMP P/N 640440-4, may be used. Pin assignments are provided in Table 2.
There are many issues to consider when packaging a power stage including capacitor selection and configuration, routing of high current connections, heat sink size, and air or liquid cooling. These issues should be considered at the design stage and if not adequately addressed, a reliable power stage may never be realized.
Capacitors should be selected with ripple current capabilities sufficient for the particular application. For safety purposes, permanent bleeder resistors should be installed across the capacitors to ensure they are discharged when the power stage is turned off. The connection from the capacitors to the IGBTs should contain as low inductance as possible. Making this connection with a laminated bus is the most effective technique for minimizing bus inductance. A laminated bus uses flat sheet conductors separated by a thin insulator to force opposing currents to cancel magnetic fields thereby minimizing the inductance of the current path.
Low inductance will minimize voltage overshoots at turn off and minimize, if not eliminate the need for snubber capacitors. The voltage overshoot should be measured under controlled pulsed conditions at the over current threshold to be sure that IGBTs will not be destroyed due to over voltages.
Stray capacitance from the electrical connections within the IGBT to its baseplate exist. The high dV/dts inherent in IGBT based power stages will conduct current through this stray capacitance that may cause the heatsinks containing the IGBTs to float to dangerously high potentials. For this reason as well as to minimize noise coupling into the GDB, it is recommended that heatsinks be grounded.
Heatsinks should be sized to dissipate the heat generated by the operation of the IGBTs. The total power loss (conduction losses and switching losses) of an IGBT power stage can be closely approximated using calculations based on IGBT and system parameters (APS applications engineers are available to assist with these calculations in certain situations). However, the calculated estimates should always be verified with empirical testing. Consult APS for heatsink and bus bar recommendations.
Figure 10: Mechanical Drawing
Figure 9 Standard current scaling, can be modified consult APS.